{"title":"A novel low-side structure for OPTVLD-SPIC technologically compatible with BiCMOS","authors":"Junji Cheng, Xingbi Chen","doi":"10.1109/ISPSD.2013.6694444","DOIUrl":null,"url":null,"abstract":"A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since this low-side structure is capable of being integrated with high-side structure and circuits on a single chip, through the low-cost self-isolation (SI) technology, it is very attractive for fabricating the smart power IC (SPIC) better and cheaper.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2013.6694444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since this low-side structure is capable of being integrated with high-side structure and circuits on a single chip, through the low-cost self-isolation (SI) technology, it is very attractive for fabricating the smart power IC (SPIC) better and cheaper.