Simulation of number of pulses to breakdown during TLP for ESD testing

Abstract

The breakdown characteristics of the gate insulator of nMOSFETs during transmission line pulsing for electrostatic discharge testing is evaluated by using device simulations. Experimental data for the gate bias and gate oxide thickness dependences of the number of pulses to breakdown are reproduced by adopting the anode-hole-injection model. The polarity of the gate bias dependence of the breakdown characteristics can be explained by the depletion of the gate electrode.