Voltage overshoots and n-MOSFET hot carrier robustness in VLSI circuits

Abstract

Capacitive coupling and charge redistribution effects in product circuits can result in large V/sub ds/ overshoots which cause much larger reductions in n-MOSFET hot carrier failure times than the transition time dependencies previously studied. Using a variety of simulations, we show that these effects can occur in typical high performance microprocessor circuits. Controlling these effects and verifying circuit compliance are key to ensuring hot carrier robust circuit design. Although we focus on n-MOSFET's a symmetrical argument can be made for p-MOSFET's.<>