PMOS Dynamic RAM Reliability = A Case Study

Abstract

This paper summarizes the history of 21,504 beam-leaded, aluminum metal PMOS 1K dynamic RAM chips through 20,000 hours in a typical telephone central office application, and predicts subsequent failure rates by extrapolation from distribution models fit to the failure data. The memory chips were processed using essentially standard PMOS silicon gate, aluminum metal technology, but with Ti-Pt-Au beam leads applied for packaging in a 22-pin, 4-chip, ceramic substrate DIP. Major failure mechanisms exhibited by the 47 chips failing during the 20,000-hour field study included gate oxide shorts, hot-electron charging of gates left floating by missing contact windows (unique to the process used for these particular devices) and parasitic MOS transistors due to thinned field dielectric. Other failures were due to various anomolous defects. Characteristics of the failure mechanisms are discussed in some detail. Failure rates beyond the 20,000-hour point are predicted by fitting several distribution models to the data. The lognormal, logarithmic extreme value and Weibull distributions all fit the data quite well, particularly when the estimate of faulty subpopulation size for each failure mechanism is optimized. Treating the failure mechanisms independently results in prediction of lower long-term failure rates than similar treatment of all failures combined. Cumulative chip failure rate through 20,000 hours was 110 FITs, and the average failure rate between 10,000 and 20,000 hours was 37 FITs. Instantaneous failure rate is projected to be less than 10 FITs after five years of field operation.