A study of hot spot in silicon device for stacked die packages

Abstract

Stacked die packages are currently used for mobile phones, digital cameras etc as a system-in-package, which includes memory and processor, the other ICs. A memory die is mounted on a processor die using an isolation material (silicon spacer or organic materials) in a package. Small hot spots of silicon devices are serious concern for device function errors, for instance, the difference of 30 degrees in a device affects device access speed error, etc. To study hot spots in a device, a thermal TEG chip, window tunnel and thermal simulation tool were used. After small hot spots were made in the thermal TEG chip packaged with a stacked die package, temperature differences in the device as a function of hot spot sizes were measured. After observing the correlation between experiments and models, a variety of stacked die package designs was studied for hot spot issue. For instance, the effect of die sizes, die thickness, spacer sizes, package types and material properties on thermal performance considering hot spot sizes. The study suggests stacked die package structures and material properties affect hot spot and thermal performance for stacked die packages. The results and explanation are described in this paper.