Potential profile engineering for quarter micron buried channel pMOSFETs with n regions in the channel

1992 International Technical Digest on Electron Devices Meeting Pub Date : 1900-01-01 DOI:10.1109/IEDM.1992.307499

K. Okabe, T. Ikezawa, I. Sakai, M. Fukuma

引用次数: 0

Abstract

A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effective for suppressing drain induced barrier lowering (DIBL) of buried channel pMOSFETs, without any degradation in Vt controllability. Simulation results suggest the potential profile engineering is useful for designing 0.25 mu m buried channel pMOSFETs with high driving capability and good Vt controllability.<>

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四分之一微米埋地沟道pmosfet的潜在剖面工程

提出了一种以电位剖面工程为特征的亚半微米深埋沟道pmosfet设计新方法，通过在LDD耗尽层内放置n个区域。新设计的n区可以有效抑制埋沟道pmosfet的漏极诱导势垒降低(DIBL)，而不会降低Vt的可控性。仿真结果表明，电位剖面工程可用于设计具有高驱动性能和良好电压可控性的0.25 μ m埋地沟道pmosfet。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1992 International Technical Digest on Electron Devices Meeting

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