Phosphorus pile-up model for SiO/sub 2/-Si interface of p-channel MOSFETs

Abstract

Dopant distribution is very important when simulating the performance of LSI devices. Therefore dopant segregation should be taken into account when it occurs to the extent that it affects this distribution. This paper suggests that for p-channel MOSFETs the "phosphorus pile-up phenomenon" should be taken into account and proposes a simulation model.