Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)

Abstract

In this study a WLCSP structure in microelectronic application is considered. In the current development of WLCSP solder post is used to bridge the die and solder bump to release part of the stress concentration caused by mismatch of Thermal Expansion Coefficient (CTE). Thermal cycle reliability analysis on solder joints with 3D finite element simulation is firstly carried out. The stress/creep strain distribution and evolution are analyzed and the fatigue lives of solder joints are estimated. Finite element model is also verified and the fatigue property of currently used solder is determined with JEDEC thermal cycle reliability test. Structure design optimization is thereafter performed to improve the reliability of WLCSP. Parametric studies on the geometry structures are carried out, such as die thickness, solder post height and solder bump diameter, etc. The results show that solder post does great help to improve the solder bumpspsila reliability, the height of which plays an important role in controlling the fatigue life of the package. Higher post helps to release the stress concentration and therefore extend the fatigue life of solder bumps. In addition, die thickness plays the most important role in affecting fatigue life of solder joints. The thinner the die, the better the reliability of WLCSP is. Other parameters, such as the diameter of the solder bump, only have tiny effect on the solder joints reliability of WLCSP.