A CMOS Reference Voltage Buffer Designed for Near-rail Voltage

Abstract

This paper presents a CMOS buffer for near-rail voltage. Compared with conventional OTA-based structure, an additional super source follower is added in the loop, which hence maintains fairly high loop-gain even when the input voltage is very close to the power supply voltage or ground. The voltage-drop between the buffered voltage and the rail can be as low as 10 mV. Besides, the output impedance can be lower as the proposed buffer entails larger load capacitor.