S. E. Liu, M. Yu, Y. Chen, J. Jao, M. Z. Lin, Y. Fang, M. Lin
{"title":"Aging of I/O overdrive circuit in FinFET technology and strategy for design optimization","authors":"S. E. Liu, M. Yu, Y. Chen, J. Jao, M. Z. Lin, Y. Fang, M. Lin","doi":"10.1109/IRPS.2016.7574592","DOIUrl":null,"url":null,"abstract":"We investigated aging property of FinFET-based I/O overdrive circuits (IP) and proposed design strategies of optimization among performance/area/reliability. Aging behavior of I/O overdrive IP with 16nm FinFET process has been extracted and compared with 20nm planar-transistor process. Both pulldown and pull-up driving degradation are worse in the FinFET than planar IP. An aging simulation framework was built from transistor-level aging databases and further calibrated by an empirical equation and IP-level measurements. Finally, a design guideline was discussed and proposed to pursue balance of performance/area/reliability, which is thus improved 13%/8%/37% respectively in our optimized design.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2016.7574592","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We investigated aging property of FinFET-based I/O overdrive circuits (IP) and proposed design strategies of optimization among performance/area/reliability. Aging behavior of I/O overdrive IP with 16nm FinFET process has been extracted and compared with 20nm planar-transistor process. Both pulldown and pull-up driving degradation are worse in the FinFET than planar IP. An aging simulation framework was built from transistor-level aging databases and further calibrated by an empirical equation and IP-level measurements. Finally, a design guideline was discussed and proposed to pursue balance of performance/area/reliability, which is thus improved 13%/8%/37% respectively in our optimized design.