A VHDL-based virtual test concept for pre-silicon test-program debug

Abstract

Tight Time-to-Market demand for System-on-Silicon (SoS) products requires innovative measures to reduce the development time in each phase, in particular for test engineering which tends to be a bottleneck in the path to engineering amples for customers. Virtual Test (VT) is a new technique able to drastically reduce the gap between first silicon and the availability of a debugged test program. VT allows debugging digital and mixed-signal test programs in a simulation environment if a fast and sufficiently accurate IC model can be made available. Behavioural model of the chips under test turned out to be a very promising approach to cover both the needs of designer for the sign-off simulation on chip level and of test engineers for VT. In this paper we demonstrate that VHDL covers all requirements of VT from the functional point of view with acceptable simulation performance.