Generic models for interconnect delay across arbitrary wire-tree networks

Abstract

New, generic and compact closed-form expressions for distributed wire-tree delay dependence on input ramp time, tree topology and wire geometries are reported. In agreement to within 5% of HSPICE simulations, these expressions permit rapid, accurate and early estimates of interconnect delay as well as variations in interconnect delay due to variations in interconnect process parameters across arbitrary distributed wire-tree networks.