{"title":"Reliability investigation upon 30 nm gate length ultra-high aspect ratio FinFETs","authors":"W. Liao, Shiao-Shien Chen, S. Chiang, W. Shiau","doi":"10.1109/RELPHY.2005.1493144","DOIUrl":null,"url":null,"abstract":"3D vertical double gate (FinFET) devices with an ultra-high aspect ratio (Si-fin height/width=H/W>7) and gate nitrided oxide (N/O) of 14/spl Aring/ have been successfully developed. This paper details reliability characterizations, including V/sub bd/, Q/sub bd/, NMOS HCI (hot carrier injection) DC and AC lifetimes as well as PMOS NBTI (negative bias temperature instability) lifetimes, which indicate robust properties for future industrial applications.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2005.1493144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
3D vertical double gate (FinFET) devices with an ultra-high aspect ratio (Si-fin height/width=H/W>7) and gate nitrided oxide (N/O) of 14/spl Aring/ have been successfully developed. This paper details reliability characterizations, including V/sub bd/, Q/sub bd/, NMOS HCI (hot carrier injection) DC and AC lifetimes as well as PMOS NBTI (negative bias temperature instability) lifetimes, which indicate robust properties for future industrial applications.