Low-power design methodology for Gbit/s bipolar LSIs

Abstract

A low-power Gbit/s operating bipolar standard cell LSI design methodology is described. It features a performance-driven layout, highly accurate static timing analysis, and CAD-based optimization for power dissipation. A 5.6-k-gate SDH signal-processing LSI operates at 1.6 Gbit/s with only 3.9 W power consumption.