The Time-dependent latch-up defect induced by single-particles in bulk CMOS

Abstract

The time-dependent latch-up defect induced by single-particles in bulk CMOS is examined. This paper presents that the latch-up defect could be caused by a time-varying negative power supply voltage on Vss terminal from single particles strike, under the precondition of the pulse peak Vss_peak0 to maintain latch-up stability. The charge Qc depends on a transient pulse width and transit time of parasitic two bipolar transistors. Subsequently, the proposed conclusions were verified by numerical transient simulation experiment.