Duty Cycle Adjustment for the Low Cost High Frequency Charge/Discharge CMOS Oscillator

Abstract

A new technique for adjusting the duty cycle in low cost 70MHz charge/discharge based oscillator topology is proposed. Added circuitry is optimized in order to maintain the frequency variation of the initial oscillator topology (without duty cycle adjustment) for a supply voltage range between 1.6V and 2V. The circuit uses different bias currents for each stage and it is implemented using Cadence design suite. It features reduces sensitivity to supply voltage range of the output frequency and low duty cycle variation.