Sub-Nanosecond Delay CMOS Active Gate Driver for Closed-Loop $\mathrm{d}v/\mathrm{d}t$ Control of GaN Transistors

Abstract

This paper presents an AGD (active gate driver) implemented with a low voltage CMOS technology to control the $\mathbf{d}\boldsymbol{v}/\mathbf{d}\boldsymbol{t}$ sequence of low voltage (100V) and high voltage (650V) GaN power transistors. Such an AGD can control and reduce the $\mathbf{d}\boldsymbol{v}/\mathbf{d}\boldsymbol{t}$ of fast switching GaN devices with a reduced impact on switching losses. In the case of both low voltage and high voltage GaN fast switching transistors, such an AGD must have a total response time lower than 1ns. Therefore, introducing a feedback loop to control the $\mathbf{d}\boldsymbol{v}/\mathbf{d}\boldsymbol{t}$ requires a specific design with a very high bandwidth (550MHz). Moreover, probing the $\boldsymbol{v}_{\mathbf{DS}}$ voltage and its derivative is quite challenging, as the voltage level is higher than the low voltage gate driver supply. The purpose of this work is to optimize a low voltage CMOS AGD with fully integrated functions, and implement such a solution in GaN-based power converters.