An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application

Abstract

An EOS-free PNP-enhanced cascoded NMOSFET structure for high voltage application is proposed. By controlling the bias of the first gate of cascoded NMOSFET, the EOS-free control circuit can not only raise the holding voltage in normal high voltage (HV) operation to prevent from the threats of EOS damages, but also retain the strong ESD robustness during ESD stress. The improved EOS immunity is successfully verified by a simple EOS-emulating test in this paper.