{"title":"Advanced geometric techniques in 3D process simulation","authors":"N.A. Golias, R. Dutton","doi":"10.1109/SISPAD.1996.865323","DOIUrl":null,"url":null,"abstract":"The modeling of semiconductor devices in the deep submicron era is a complicated and challenging procedure. Due to continuous scaling of IC structures many physical effects pose requirements for a full 3D simulation. The incorporation of advanced computational geometry techniques is imperative in the realization of such 3D process simulation tools. The simulation of a virtual factory, with the various processing steps (ion implantation, diffusion, oxidation, etching and deposition) directly modeled on a 3D tetrahedral grid presents many advantages, such as the direct geometry extraction for subsequent interconnect analysis and device simulation. Advanced geometric techniques for the realization of a virtual IC fabrication simulator directly on a 3D tetrahedral grid are presented. A highly efficient algorithm for refining unstructured tetrahedral meshes, having an O(n) computational complexity which generate very high quality elements, is used as the main tool for adaptive mesh generation. Techniques for the automatic grid formation based on the mask layout and processing information and deposition of material layers are also presented.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.1996.865323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The modeling of semiconductor devices in the deep submicron era is a complicated and challenging procedure. Due to continuous scaling of IC structures many physical effects pose requirements for a full 3D simulation. The incorporation of advanced computational geometry techniques is imperative in the realization of such 3D process simulation tools. The simulation of a virtual factory, with the various processing steps (ion implantation, diffusion, oxidation, etching and deposition) directly modeled on a 3D tetrahedral grid presents many advantages, such as the direct geometry extraction for subsequent interconnect analysis and device simulation. Advanced geometric techniques for the realization of a virtual IC fabrication simulator directly on a 3D tetrahedral grid are presented. A highly efficient algorithm for refining unstructured tetrahedral meshes, having an O(n) computational complexity which generate very high quality elements, is used as the main tool for adaptive mesh generation. Techniques for the automatic grid formation based on the mask layout and processing information and deposition of material layers are also presented.