Signal integrity for USB 3.1 Gen 2 front end challenging loss budget

Abstract

This works presents rigorous full-wave modeling efforts to meet the design challenges and tight loss budget allowed for protocol analyzer intended for USB 3.1 Gen 2.0 operating at 10 Gbps. The design cycle starts from the basic foundation of building a robust stackup for high quality signal integrity for high speed applications using ANSYS HFSS. The models do include the actual manufacturing design parameters and constrains of fab house. This is very imperative to guarantee a properly working first prototype and to eliminate the hassle of several prototype iterations. Impedance, losses, via transition, discontinuities, cross talk, and layout routing are all optimized to meet the challenging requirements of front end loss budget for USB protocol analyzer. Experimental measurements are presented to validate the simulation results.