Impact of Random Phase Distribution in 3D Vertical NAND Architecture of Ferroelectric Transistors on In-Memory Computing

Abstract

Ferroelectric field-effect transistors (FeFETs) with 3D vertical NAND architecture (3D V-NAND) are investigated for in-memory computing. In polycrystalline ferroelectric Hafnia thin film, there are different phases such as monoclinic (M), and orthorhombic (O) phases. Those are randomly distributed throughout the ferroelectric gate stack. Such positional dispersion of two phases introduces read-out current variation in 3D V-NAND of FeFETs. Herein, we employ TCAD simulations to quantify such variation and optimize bias conditions for improving the accuracy of in-memory computing.