Determination of CPU use conditions

Abstract

Use condition inputs to physics-of-failure models are required to use knowledge-based qualification of ICs. Modern CPUs have multiple voltage-frequency states which vary widely in reliability stress, but it is not obvious what time in the various states to use in product qualification. We present a methodology for developing a time in state model for CPUs which combines large scale user monitoring and lab-based studies. Results for a specific CPU family, including field validation and implications for knowledge-based qualification, are discussed.