Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution

Abstract

We propose an area-efficient and low-cost extraction methodology of Vth variation which utilizes the exponential relationship of gate delay to Vth variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to Vth variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. Vth variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. Vth variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of Vth variation.