Circuit and System Design for a Homodyne W-CDMA Front-End Receiver RF IC

Abstract

This paper discusses the RF circuit and system design considerations for W-CDMA homodyne receiver on NF, IIP2, IIP3, LO/TX leakage, I-Q mismatch, DC offsets, etc. A zero-IF receiver front-end SiGe BiCMOS IC is designed, packaged and thoroughly characterized by a set of system-level performance tests across the full frequency band of operation. The measured worst-case cascaded NF for the receiver IC across all channels is 4.3 dB at the max. gain mode, and the in-band/out-of-band IIP2 and IIP3 are +37/+93 and -16.5/+5 dBm, respectively. The I/Q channels exhibit a small mismatch in magnitude (<0.1dB) and in phase (<1deg) without calibration. The receiver RF front-end (i.e., LNA+VGA+ I/Q mixers) draws ~45mW. The system tests results on BER, P1dB, IM2, IM3, and desensing show that the RFIC meets all of the necessary parameters of W-CDMA receiver system specs at room temperature with margin, validating the RF IC block-level circuit design and providing valuable RF-SoC design insights