SI and EMI analysis of analog circuit board combination of PEEC and MOR

Abstract

A method for analyzing SI and EMI of an analog circuit board considering the effect of analog patterns has been proposed. This method uses the combination of PEEC (partial element equivalent circuit) and MOR (model order reduction). Major contributors to signal, power and EMI noise in high power supply circuits are the parasitics of arbitrary shape conductor patterns between discrete components such as power MOS transistors and passive components. The conductor patterns are modeled as meshed RLGC network circuits, and then compressed into a compact circuit model. Voltage and current waveforms in the time domain and EMI in the frequency domain are simulated by using the obtained macro model and nonlinear devices.