Reducing analogue fault-simulation time by using ifigh-level modelling in dotss for an industrial design

Abstract

A crucial issue for using defect-oriented testing in analogue testing is how to reduce the massive faultsimulation time. One solution to this problem is to use high-level models in the fault simulation. However, the high-level model used in fault simulations has diferent requirements as compared to the high-level model normally used in IC design. This is because the behaviour of the faulty block is unknown and it is possible that it works totally diflerent from the fault-ffee one. In this paper, a new general structure of a high-level model with three stages is proposed. The approach has been applied to the RECEIVER block of an industrial chip. The fault simulations with this high-level model have been carried out with Dotss, an industrial analogue fault simulation and test optimisation tool based on defect-oriented testing. The results show that this kind of high-level models can work properly in fault simulations and effectively reduce the fault-simulation time.