{"title":"Thermo-mechanical Stress of underfilled 3D IC packaging","authors":"Ming-Han Wang, Mei-Ling Wu","doi":"10.1109/EUROSIME.2014.6813801","DOIUrl":null,"url":null,"abstract":"In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different thermal expansion. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1-9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4-9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the structure to be simulated from the temperature 150°C to -50°C which is as retreat temperature. This paper use ANSYS software which is based on finite element theory in order to reduce time used and save cost, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the maximum von-Mises stress in TSVs and micro-bumps. Besides, this paper will sort out geometries and material properties of underfill which will serious affect von-Mises stress value by Design of Experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von-Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.","PeriodicalId":359430,"journal":{"name":"2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUROSIME.2014.6813801","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different thermal expansion. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1-9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4-9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the structure to be simulated from the temperature 150°C to -50°C which is as retreat temperature. This paper use ANSYS software which is based on finite element theory in order to reduce time used and save cost, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the maximum von-Mises stress in TSVs and micro-bumps. Besides, this paper will sort out geometries and material properties of underfill which will serious affect von-Mises stress value by Design of Experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von-Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.
近年来,由于越来越多的各种功能被集成到设备中,并且产品的尺寸变得越来越小,有关电子产品的研究急剧增加。基于这些功能需求,通过硅通孔(TSV)进行研究,不仅可以减小封装尺寸,而且可以缩短互连距离,从而达到增强信号传输的效果。tsv是穿过堆叠IC的垂直孔,它们也负责在IC之间传输信号。因此,它们可以改善信号转导的时间延迟,并且比采用线键合技术的堆叠ic具有更好的电气性能。然而,回顾文献表明,电子元件将容易受到环境因素,如湿度,压力和温度的影响。通常,由于每种材料的热膨胀率不同,TSV结构的堆叠集成电路容易受到温度变化的影响。近年来,与传统的单芯片封装相比,堆叠封装主要关注的是热机械载荷,这导致了一些问题,如通孔开裂、模具开裂和界面分层等。以上问题不仅会影响设备的性能,还会导致设备故障。因此,大多数研究[1-9]都集中在用模拟方法讨论热机械载荷。其中一些讨论了TSV形状与应力之间的关系[4,5]。此外,大多数人只是建立当地的TSV结构来进行研究[4-9]。虽然可以节省更多的时间,但也增加了与实际情况的错误率。本文以Hsieh b[1]的论文为基础,建立了更接近实际情况的三维四层堆叠IC封装模型。并将待模拟结构的温度设置为150℃至-50℃,即后退温度。本文采用基于有限元理论的ANSYS软件,由于有限元仿真可以比实验更快、更便宜地提供结果,从而减少了使用时间,节约了成本。此外,研究重点分析了tsv和微凸起的最大von-Mises应力。此外,本文还将通过试验设计(Design of Experiments, DoE)分析对影响von-Mises应力值的下填体几何形状和材料特性进行梳理。通过DoE分析,选择关键因素作为减小von-Mises应力的主要设计因素。该研究可为有效设计产品、提高产品可靠性提供重要信息。这些信息还可以减少测试时间。