Electro-thermal analysis of device interactions in Si CMOS structure

Abstract

Numerical calculation of submicron silicon MOSFET and CMOS device is performed. Conjugate nature of the thermal and electrical behavior in the device is considered, and the lattice temperature is solved as well as the electron concentration and the electron temperature. Considering both the electron temperature and the lattice temperature is important for the device modeling, for example the electron distribution shows the difference with and without considering the electron temperature. In this research, by comparing the calculation result of n-type and p-type MOSFET and that of CMOS, we examine the interaction mechanism between n-type and p-type MOSFET in CMOS device when the distance between n-type and p-type MOSFET is decreased. From the calculated results, we investigate that the reason of the interaction between two MOSFET in CMOS is the forward bias at the p-n junction of substrate. Furthermore, we can estimate the distance, at the case of interaction, from the results of n-type and p-type MOSFET separately model, not from the results of CMOS model.