The importance of retardation in PEEC models for electrical interconnect and package (EIP) applications

A. Ruehli, E. Chiprout
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引用次数: 4

Abstract

Partial Element Equivalent Circuit (PEEC) models have been employed in both the EMI (Electro-Magnetic Interference) as well as the EIP (Electrical Interconnect and Package) areas. It is generally assumed that the retardation between the circuit elements can be ignored for EIP problems since the radiated fields are not of interest for this application. In this paper, we give some insight into the importance of retardation for EIP problems.
延迟在电气互连和封装(EIP)应用的PEEC模型中的重要性
部分元件等效电路(PEEC)模型已被用于EMI(电磁干扰)和EIP(电气互连和封装)领域。通常假设电路元件之间的延迟可以忽略,因为辐射场对这种应用不感兴趣。在本文中,我们对智力发育迟缓在经济知识产权问题中的重要性进行了一些探讨。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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