ESD phenomena in graded junction devices

Abstract

The current very large-scale integration (VLSI) chips for sub-2- mu m processes use some form of graded junction devices for process reliability. Electrostatic discharge (ESD) performance for these graded junction processes is examined by studying the process variations. The results show that the ESD protection level can be optimized without significantly compromising the hot carrier reliability or the circuit drive current. The unique failure modes in these devices are also discussed. The results are supported by transient thermal analysis simulations.<>