A 0.18 /spl mu/m 4 Mbit toggling MRAM

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309899

M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani

引用次数: 3

Abstract

A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.

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一个0.18 /spl mu/m 4 Mbit可切换MRAM

介绍了一种具有新型磁开关模式的4mbit磁阻随机存取存储器(MRAM)。存储单元基于1晶体管1磁隧道结(1T1MTJ)位单元。4 Mbit MRAM电路采用5级金属、0.18 /spl mu/m CMOS工艺设计，位元尺寸为1.55 /spl mu/m/sup 2/。与传统MRAM相比，新的单元结构、位结构和交换模式提高了MRAM的操作性能。4mbit电路是迄今为止最大的MRAM存储器演示。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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