Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects

Abstract

In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induced variations lead to different sizes of crosstalk defects. The largest crosstalk defects are detected by conventional interconnect test methods, while the smaller ones do not change the system behavior and are left without detection. In this paper, we show that even smaller crosstalk defects have an inevitable impact on electro-migration (EM) degradation. They increase the current that conveys through the wire and consequently result in more EM degradation and shorter mean time to failure of the system. Simulation results show that in the worst case the EM degradation increases up to 90%, however, even in the normal situation 7.2% degradation can be observed for the PARSEC 2000 benchmark Because these Hidden Interconnect Defects cause different small delay sizes, we propose a multi-frequency test method to detect them properly. Our experimental results for 8000 different 32-bit interconnect layouts show that, on average, 6 frequencies and 81 test patterns are required for finding hidden interconnect defects.