Predicting large-signal CML gate delay using Y-Parameters for fast process optimization

Abstract

A Y-Parameter based Figure-of-Merit (FoM) is proposed that can accurately predict large-signal Current-Mode Logic (CML) gate delay from small-signal S-parameter simulations/measurements. A differential-mode (DM) half circuit of an emitter-coupled differential pair with resistive load is used as the small-signal building block. The FoM is applied to various collector current (IC) and load resistor (RL) combinations obtained from the power-delay curve of a prototype SiGe technology platform. Results of the FoM delay predictions are compared with ring oscillator gate delays. A small-signal model parameter based equation is also proposed that provides physical insight into the components that contribute to the overall CML delay.