Challenge of vacuum molded flip chip packaging technology

K. Chai, E. Wu, J. Tong
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引用次数: 4

Abstract

To be the solution of higher throughput, uniform outline and level up reliability performance of mature capillary underfill packaging, molded underfill technology is studied by assembly houses, equipment vendors and material manufactures for years and is expected to be the major assembly method of flip chip package in the future. Vacuum molding flip chip packaging technology is one developed by lots of molding equipment vendors from various molded underfill theories, and the key issues are the uncompleted fill under the die and the flush at vacuum position(s). Finer filler (less than 10 /spl mu/m particle size) compound is used for the small gap between chip and substrate & the clearance of flip chip bumps, but we still need to ensure that there is no air be trapped under the die during molding process. Vacuum parameter and position are also very important to avoid the uncompleted fill and material flush from air vent areas. Siliconware is now developing such technology as an alternative solution of capillary underfill flip chip packaging. The test vehicle and vacuum processing technology development by tuning the parameters and modifying the mold chase design will be simply introduced here, and the reliability test is going to confirm the package performance.
真空模制倒装芯片封装技术的挑战
为了解决成熟的毛细管下填充封装更高的吞吐量、均匀的轮廓和更高的可靠性性能,组装厂、设备供应商和材料制造商对模压下填充技术进行了多年的研究,并有望成为未来倒装封装的主要组装方法。真空模制倒装芯片封装技术是众多模制设备厂商在各种模制下填充理论的基础上发展起来的一项技术,其关键问题是模下填充未完成和真空位置的齐平。对于芯片和基板之间的小间隙和倒装芯片凸起的间隙,我们使用了更细的填料(小于10 /spl mu/m粒度)化合物,但我们仍然需要确保在成型过程中模具下没有空气被捕获。真空参数和位置也非常重要,以避免未完成的填充和材料从排气口区域冲刷。Siliconware现在正在开发这种技术,作为毛细管下填充倒装芯片封装的替代解决方案。本文将简单介绍通过调整参数和修改模座设计来开发的试验车辆和真空加工技术,并对封装性能进行可靠性试验。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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