Mold Flow Analysis of a SiP Package for Power Management

Abstract

At present, System in Package (SiP) is getting more and more applications in power packages. Due to the complexity of the packages, the molding process becomes crucial for the yield and reliability of the products. During the transfer molding process, the packaging processes of the packages may introduce assembly defects, such as void, wire sweep, warping, etc. To determine the main factors is one of the most important measures to eliminate and prevent these defects.In this paper, 3D Molding flow simulation for the SiP package is conducted by using the Moldflow software with the aim to predict the location of the void and weld line during the plastic package process. The influence of gate design on process-induced defects and other reliability issues was studied. The results show that the filling of different gate locations in the package will produce cavitation defects at different locations. A gate design with fewer corners in the injection direction will produce fewer cavitation. Increasing the number of gates will reduce air pockets at the corners, but will cause more air pockets near the weld line. When the gate position is perpendicular to the top surface of the chip, less weld marks are generated. The flow front will produce weld marks after being blocked. When the number of gates increases, the area of the flow front increases and the number of weld lines increases significantly.