Multi-voltage device integration technique for 0.5 /spl mu/m BiCMOS and DMOS process

Abstract

This paper describes the multi-voltage device integration technique for BiCMOS and DMOS process and the simple measures to the beta decreasing of 5 V/12 V NPNTr by the lack of heat treatment used for half-micron process. The N well offset gate are used for 30 V HV-NMOS. Moreover, RESURF effect by Buried P+ is applied to 60 V HV-NMOS. Each specific on-resistance (Ron/spl middot/S) reaches sufficiently low value (60 m /spl Omega/ mm2 (BVds=33 V), 127 m /spl Omega/ mm2 (BVds=74 V)). 60 V DMOS structure became to 90 V DMOS by only addition of P well guard ring, and the Ron/spl middot/S is 230 m /spl Omega/ mm2 (BVds=94 V). Using the appropriate length of RESURF formed at N-epitaxial layer; we could optimize 30 V/60 V/90 V NMOS devices and FID (Full Isolation Diode). In the case of PMOS, 30 V/60 V/90 V PMOS has been realized by using the combination of P-LDD (Lightly Doped Drain) and Sinker P region (P body, P well). Using a P+ shield region stabilized the beta of 5 V/12 V NPNTr. Any complicated process step is not needed for various techniques mentioned above.