Design and process optimization for dual row QFN

Abstract

The continuous advancement in technology and miniaturization of electronic components, hand held and communication devices require superior thermal-electrical performance and miniature packages. An advanced and complicated Integrated Circuit (IC) device often demands increase in number of I/O's while maintaining its small size, footprint and weight. Dual Row Quad Flat No lead (DR-QFN) is an ideal solution for such demanding applications; however, despite the simplicity of its package structure, it possesses challenges in various assembly processes. This paper describes the problems that are associated with the different concepts of both `saw' and `punch' singulated DR-QFN and the corresponding solutions to overcome the barriers. Lead isolation or separation of 1st and 2nd row of leads has always been the major challenge for saw singulated DR-QFN (DR-QFN- S) where solder burr and leadfinger delamination are inherent. Shorting between inner and outer leads during SMT is also apparent. This paper demonstrates the study on different leadframe designs and how the solutions were derived. Through modeling, the impact on solder joint reliability for the different leadframe design and the respective surface mount behavior was also explored. The primary focus in designing punch singulated DR-QFN (DR-QFN-P) is to do away with lead isolation, which is to maintain its simplicity and cost effectiveness. The key factor is the design of the leadframe and the etching capability of the manufacturer. But despite the absence of lead isolation process, DR-QFN-P similarly comes with challenges such as solder bridging and lead-to-lead short. Further in this paper describes the approach taken to overcome issues associated with this package