Design and implementation of the POWER5/spl trade/ microprocessor

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332591

J. Clabes, J. Friedrich, M. Sweet, Jack DiLullo, S. Chu, D. Plass, James Dawson, P. Muench, Larry Powell, Michael Floyd, B. Sinharoy, Mike Lee, Michael Goulet, J. Wagoner, N. Schwartz, S. Runyon, Gary Gorman, Phillip Restle, R. Kalla, J. McGill, S. Dodson

{"title":"Design and implementation of the POWER5/spl trade/ microprocessor","authors":"J. Clabes, J. Friedrich, M. Sweet, Jack DiLullo, S. Chu, D. Plass, James Dawson, P. Muench, Larry Powell, Michael Floyd, B. Sinharoy, Mike Lee, Michael Goulet, J. Wagoner, N. Schwartz, S. Runyon, Gary Gorman, Phillip Restle, R. Kalla, J. McGill, S. Dodson","doi":"10.1109/ISSCC.2004.1332591","DOIUrl":null,"url":null,"abstract":"POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332591","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 25

Abstract

POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets.

查看原文本刊更多论文

POWER5/spl交易微处理器的设计与实现

POWER5/sup TM/是IBM的下一代POWER微处理器。该设计通过结合同步多线程(SMT)、支持164w SMP的增强型分布式交换机和内存子系统以及广泛的RAS支持，设定了服务器性能的新标准。采用IBM 130纳米绝缘体上硅技术的首通硬件在1.3V下工作在1.5GHz以上。POWER5的双线程SMT为每个核心创建最多两个虚拟处理器，从而提高了执行单元利用率并屏蔽了内存延迟。虽然简单的SMT实现承诺/spl sim/20%的性能提高，但在许多情况下，调整关键微架构资源的大小几乎可以使SMT性能提高一倍，达到24%。实现这些微架构增强在满足芯片的频率、面积、功率和热目标方面提出了挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

自引率

0.00%

发文量