Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing

Abstract

Critical charge to represent a logic HIGH is steadily decreasing with decreasing technology feature size. Many methods have been developed to increase critical charge requirement for storage elements, thereby reducing the soft error rates. Design-based approaches have been proposed that use four storage nodes instead of two nodes to retain data. Such designs are considered single event upset (SEU) immune at low energy ion hits for all practical purposes because a single ion hit at a storage node does not cause an upset. However, such designs are vulnerable to ion hits that result in multiple nodes collecting charges. For deep sub-micron technologies, the proximity of circuit nodes results in charge collection at multiple nodes when a single ion strikes a node. Researchers first observed the effect of such charge sharing in SRAM designs. In this paper, circuit and 3D technology computer aided design (TCAD) mixed-mode simulations are used to characterize charge sharing between sensitive pairs of devices and the resulting upsets in a hardened storage cell. The simulation results were verified with experimental data showing upsets due to charge sharing in a hardened cell when exposed to low energy ions