Interconnect Scaling Scenario Using A Chip Level Interconnect Model

Abstract

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio, pitch at each layer and improved circuit design techniques as well as new interconnect materials. A new design methodology for interconnect at a chip level is proposed. It is found that high performance VLSI in the 0.13bm CMOS generation needs 6 number of metal layers using Cu interconnect and low-k materials.