A 1.8/2.6 GHz CMOS high linearity power amplifier for LTE application

Abstract

This paper presents a CMOS high linearity power amplifier for LTE application. We use inverter circuits and t second harmonic control to improve the linearity. This circuit will be processed with TSMC 0.18 μm technology. The simulation result shows that the circuit exhibited a power gain of 25.9 dB, an input return loss less than - 20.2/20.9dB, the PAE is about 35%/31.2% and the output power is about 21.6/18.2 dBm at 1.8/2.6GHz. The power consumption is 378mW at voltage of 3.3V.