Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application

Y. Liu, T. Mastukawa, K. Endo, S. Oruchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura
{"title":"Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application","authors":"Y. Liu, T. Mastukawa, K. Endo, S. Oruchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura","doi":"10.1109/ESSDERC.2011.6044199","DOIUrl":null,"url":null,"abstract":"The threshold voltage (V<inf>t</inf>) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior I<inf>d</inf>-V<inf>g</inf> characteristics are observed in the scaled poly-Si channel FinFETs with gate length (L<inf>g</inf>) down to 54 nm or less. The standard deviation of V<inf>t</inf> (σV<inf>t</inf>) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (T<inf>ox</inf>). However, the σV<inf>t</inf> of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even L<inf>g</inf> was down to 76 nm.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2011.6044199","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.
用于高密度和低成本堆叠3d存储器应用的缩放多晶硅通道finfet和三门闪存的可变性分析
本文首次系统地比较了多晶硅通道finfet和多晶硅浮栅三栅极闪存的阈值电压(Vt)与晶体通道的阈值电压(Vt)。结果表明,栅极长度(Lg)小于等于54 nm的多晶硅沟道finfet具有优越的Id-Vg特性。在相同栅极氧化物厚度(Tox)下,多晶硅沟道finfet的Vt (σVt)标准差是晶体沟道finfet的3倍。而多晶硅通道三栅极闪存经过一个程序/擦除(P/E)周期后的σVt与晶体通道闪存相当。此外,发现即使Lg降低到76 nm,多晶硅通道三栅极闪存的击穿电压也高达4.6 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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