Boosting off-chip interconnects through power line communication

Abstract

The number of available pins on SOC is one of the limiting factors to the off-chip bandwidth, for example many-core enabled Internet of Things (IoT) devices, where the package size and PCB floorplan are tightly constrained. A typical SOC package allocates more than half of the pins for power delivery, resulting in the number of IO pins for off-chip communications is greatly reduced. We observe the requirement for the number of power and ground (P/G) pins is driven by the highest performance state and the worst design corners, while SOC is in lower performance state for most of the time for longer battery life. Under observation, we propose to reuse some of the power pins as dynamic power/signal pins for off-chip data transmissions to increase the off-chip bandwidth during SOC low performance state. Our proposed method provides 30Gbps bandwidth per hybrid pair, while managing minimum impact to the original power delivery network (PDN) design.