High speed, low-power CMOS voltage buffers

Abstract

The standard implementation of a voltage buffer uses a two-stage opamp with total negative feedback; this results in good linearity and low output impedance but also in bandwidth reduction and stability problems. This paper presents several results of a different approach: one stage, class AB configurations, operating in open-loop or at most having some internal feedback. Three such configurations are compared: the simple complementary source follower and two combinations of the complementary source follower and common source stages, the latter driven by supplementary error opamps or directly by the source follower. The three buffers were designed for low-voltage, low-power and optimised for speed. Their bandwidth, output impedance and total harmonic distortion are compared under equal conditions of voltage supply and power consumption. Also, the possibility of driving capacitive loads and the implementation of CCII+ are discussed.