Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via

H. Shinkawata, Nobuo Tsuboi, A. Tsuda, Shingo Sato, Yasuo Yamaguchi
{"title":"Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via","authors":"H. Shinkawata, Nobuo Tsuboi, A. Tsuda, Shingo Sato, Yasuo Yamaguchi","doi":"10.1109/ICMTS.2015.7106112","DOIUrl":null,"url":null,"abstract":"We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.
针对互连孔软故障检测的窄划线线压缩双嵌套阵列的研制
介绍了一种用于量产阶段的新型可寻址测试结构阵列,即窄划线线压缩双嵌套阵列,称为划线线高灵敏度筛选检测解码测试结构(HSD-S)。在40nm CMOS技术中检测到异常高电阻作为软失效通孔。我们捕获了一个软失效钻头,通过展示超过160倍的高电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信