A holistic approach to process co-optimization for through-silicon via

Abstract

As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.