FinFET resistance mitigation through design and process optimization

Cindy Wang, Josephine B. Chang, Chung-Hsun Lin, Arvind Kumar, A. Gehring, Jin Cho, A. Majumdar, A. Bryant, Z. Ren, Kevin K. H. Chan, T. Kanarsky, Xinlin Wang, O. Dokumaci, M. Guillorn, M. Khater, Qingyun Yang, Xi Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Ying Zhang, Dae-gyu Park, C. Ouyang, W. Haensch
{"title":"FinFET resistance mitigation through design and process optimization","authors":"Cindy Wang, Josephine B. Chang, Chung-Hsun Lin, Arvind Kumar, A. Gehring, Jin Cho, A. Majumdar, A. Bryant, Z. Ren, Kevin K. H. Chan, T. Kanarsky, Xinlin Wang, O. Dokumaci, M. Guillorn, M. Khater, Qingyun Yang, Xi Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Ying Zhang, Dae-gyu Park, C. Ouyang, W. Haensch","doi":"10.1109/VTSA.2009.5159323","DOIUrl":null,"url":null,"abstract":"The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.
通过设计和工艺优化降低FinFET电阻
由于优越的静电性能,在22nm技术节点上,与平面fet相比,本质FinFET器件结构可以提供大约10-20%的延迟减少。然而,由于薄体通道和三维器件结构,finfet更容易产生寄生电阻和电容。在这里,我们提出了最小化FinFET寄生电阻的策略,并讨论了整体器件设计优化。使用45纳米节点尺寸的finfet,我们展示了具有230/350外部电阻Ω-um的finfet / fet。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信