Novel decoupling capacitor designs for sub-90nm CMOS technology

Abstract

On-chip decoupling capacitors are generally used to reduce power supply noise. Traditional decoupling capacitor designs using NMOS devices may no longer be suitable for 90nm CMOS technology due to increased concerns on thin-oxide gate leakage and electrostatic discharge (ESD) reliability. A cross coupled design for standard cells have recently been proposed to address the ESD issue. In this paper, three modifications of the cross coupled design are introduced and the tradeoffs among ESD performance, transient response and gate leakage are analyzed. As shown here, the modifications offer designers greater flexibility in decoupling capacitor design for 90nm and below