Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification

J. Karp, M. Hart, M. Fakhruddin, V. Kireev, Phoumra Tan, D. Tsaggaris, Mini Rawat
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引用次数: 2

Abstract

Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.
具有自保护ESD的芯片间接口介面FPGA设计及其CDM规范
提出了将S20.20-2014标准的200V CDM电压规范与芯片间接口的实际100-200mA CDM峰值电流联系起来的方法。在3D/2.5D装配过程中,摩擦学被认为是裸模上电荷积累的来源。介绍了裸模自电容作为三维/2.5维装配环境下的CDM建模参数。关于S20.20-2014标准的HBM/CDM资格证明用于第二代20nm中间层FPGA中的自保护模对模IOs。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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