J. Karp, M. Hart, M. Fakhruddin, V. Kireev, Phoumra Tan, D. Tsaggaris, Mini Rawat
{"title":"Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification","authors":"J. Karp, M. Hart, M. Fakhruddin, V. Kireev, Phoumra Tan, D. Tsaggaris, Mini Rawat","doi":"10.1109/IRPS.2016.7574556","DOIUrl":null,"url":null,"abstract":"Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2016.7574556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.