Process development of Large Size Embedded Silicon Fan-out (eSiFO) Package

Abstract

With the development of new technologies such as IoT, 5G, AI&VR, automotive electronics, the urgent demand of high density, multichip integration packaging technology is increasing strongly. Fan-out technology has attracted much more attentions as a new advanced technology and grown explosively. The market scale of fan-out packaging is expected to grow to 3.8 billion US dollars with a CAGR of 19% in the next few years. In this paper, one package in a size of 20×20 mm and containing a 14×14mm large embedded die was successfully manufactured. Various key process such as cavity etching, die attach, vacuum lamination were developed. A test vehicle composed of several electrical measurement structures was designed with three different thicknesses: 70 um, 80 um and 90 um, which respectively realize different package thickness. In the test vehicles, daisy chains and other test units were established to measure electricity performance.